Cmos Sram Circuit Design And Parametric Test In Nano-scaled Technologies: Process-aware Sram Design And Test (frontiers In Electronic Testing)
by Andrei Pavlov /
2008 / English / PDF
7.8 MB Download
The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.
