Design-for-test And Test Optimization Techniques For Tsv-based 3d Stacked Ics
by Krishnendu Chakrabarty /
2013 / English / PDF
6.6 MB Download
This book describes innovative techniques to address the testing
needs of 3D stacked integrated circuits (ICs) that utilize
through-silicon-vias (TSVs) as vertical interconnects. The authors
identify the key challenges facing 3D IC testing and present
results that have emerged from cutting-edge research in this
domain. Coverage includes topics ranging from die-level wrappers,
self-test circuits, and TSV probing to test-architecture design,
test scheduling, and optimization. Readers will benefit from an
in-depth look at test-technology solutions that are needed to make
3D ICs a reality and commercially viable.
This book describes innovative techniques to address the testing
needs of 3D stacked integrated circuits (ICs) that utilize
through-silicon-vias (TSVs) as vertical interconnects. The authors
identify the key challenges facing 3D IC testing and present
results that have emerged from cutting-edge research in this
domain. Coverage includes topics ranging from die-level wrappers,
self-test circuits, and TSV probing to test-architecture design,
test scheduling, and optimization. Readers will benefit from an
in-depth look at test-technology solutions that are needed to make
3D ICs a reality and commercially viable.
