Finite State Machine Datapath Design, Optimization, And Implementation (synthesis Lectures On Digital Circuits And Systems)
by Justin Davis /
2008 / English / PDF
5.5 MB Download
Finite State Machine Datapath Design, Optimization, and
Implementation explores the design space of combined FSM/Datapath
implementations. The lecture starts by examining performance issues
in digital systems such as clock skew and its effect on setup and
hold time constraints, and the use of pipelining for increasing
system clock frequency. This is followed by definitions for latency
and throughput, with associated resource tradeoffs explored in
detail through the use of dataflow graphs and scheduling tables
applied to examples taken from digital signal processing
applications. Also, design issues relating to functionality,
interfacing, and performance for different types of memories
commonly found in ASICs and FPGAs such as FIFOs, single-ports, and
dual-ports are examined. Selected design examples are presented in
implementation-neutral Verilog code and block diagrams, with
associated design files available as downloads for both Altera
Quartus and Xilinx Virtex FPGA platforms. A working knowledge of
Verilog, logic synthesis, and basic digital design techniques is
required. This lecture is suitable as a companion to the synthesis
lecture titled Introduction to Logic Synthesis using Verilog HDL.
Finite State Machine Datapath Design, Optimization, and
Implementation explores the design space of combined FSM/Datapath
implementations. The lecture starts by examining performance issues
in digital systems such as clock skew and its effect on setup and
hold time constraints, and the use of pipelining for increasing
system clock frequency. This is followed by definitions for latency
and throughput, with associated resource tradeoffs explored in
detail through the use of dataflow graphs and scheduling tables
applied to examples taken from digital signal processing
applications. Also, design issues relating to functionality,
interfacing, and performance for different types of memories
commonly found in ASICs and FPGAs such as FIFOs, single-ports, and
dual-ports are examined. Selected design examples are presented in
implementation-neutral Verilog code and block diagrams, with
associated design files available as downloads for both Altera
Quartus and Xilinx Virtex FPGA platforms. A working knowledge of
Verilog, logic synthesis, and basic digital design techniques is
required. This lecture is suitable as a companion to the synthesis
lecture titled Introduction to Logic Synthesis using Verilog HDL.
