Fundamentals Of Bias Temperature Instability In Mos Transistors: Characterization Methods, Process And Materials Impact, Dc And Ac Modeling (springer Series In Advanced Microelectronics)
by Souvik Mahapatra /
2015 / English / PDF
20.7 MB Download
This book aims to cover different aspects of Bias Temperature
Instability (BTI). BTI remains as an important reliability
concern for CMOS transistors and circuits. Development of BTI
resilient technology relies on utilizing artefact-free stress and
measurement methods and suitable physics-based models for
accurate determination of degradation at end-of-life and
understanding the gate insulator process impact on BTI. This book
discusses different ultra-fast characterization techniques for
recovery artefact free BTI measurements. It also covers different
direct measurements techniques to access pre-existing and newly
generated gate insulator traps responsible for BTI. The book
provides a consistent physical framework for NBTI and PBTI
respectively for p- and n- channel MOSFETs, consisting of trap
generation and trapping. A physics-based compact model is
presented to estimate measured BTI degradation in planar Si
MOSFETs having differently processed SiON and HKMG gate
insulators, in planar SiGe MOSFETs and also in Si FinFETs. The
contents also include a detailed investigation of the gate
insulator process dependence of BTI in differently processed SiON
and HKMG MOSFETs. The book then goes on to discuss
Reaction-Diffusion (RD) model to estimate generation of new traps
for DC and AC NBTI stress and Transient Trap Occupancy Model
(TTOM) to estimate charge occupancy of generated traps and their
contribution to BTI degradation. Finally, a comprehensive NBTI
modeling framework including TTOM enabled RD model and hole
trapping to predict time evolution of BTI degradation and
recovery during and after DC stress for different stress and
recovery biases and temperature, during consecutive arbitrary
stress and recovery cycles and during AC stress at different
frequency and duty cycle. The contents of this book should prove
useful to academia and professionals alike.
This book aims to cover different aspects of Bias Temperature
Instability (BTI). BTI remains as an important reliability
concern for CMOS transistors and circuits. Development of BTI
resilient technology relies on utilizing artefact-free stress and
measurement methods and suitable physics-based models for
accurate determination of degradation at end-of-life and
understanding the gate insulator process impact on BTI. This book
discusses different ultra-fast characterization techniques for
recovery artefact free BTI measurements. It also covers different
direct measurements techniques to access pre-existing and newly
generated gate insulator traps responsible for BTI. The book
provides a consistent physical framework for NBTI and PBTI
respectively for p- and n- channel MOSFETs, consisting of trap
generation and trapping. A physics-based compact model is
presented to estimate measured BTI degradation in planar Si
MOSFETs having differently processed SiON and HKMG gate
insulators, in planar SiGe MOSFETs and also in Si FinFETs. The
contents also include a detailed investigation of the gate
insulator process dependence of BTI in differently processed SiON
and HKMG MOSFETs. The book then goes on to discuss
Reaction-Diffusion (RD) model to estimate generation of new traps
for DC and AC NBTI stress and Transient Trap Occupancy Model
(TTOM) to estimate charge occupancy of generated traps and their
contribution to BTI degradation. Finally, a comprehensive NBTI
modeling framework including TTOM enabled RD model and hole
trapping to predict time evolution of BTI degradation and
recovery during and after DC stress for different stress and
recovery biases and temperature, during consecutive arbitrary
stress and recovery cycles and during AC stress at different
frequency and duty cycle. The contents of this book should prove
useful to academia and professionals alike.
