High-level Estimation And Exploration Of Reliability For Multi-processor System-on-chip (computer Architecture And Design Methodologies)
by Zheng Wang /
2017 / English / PDF
19.4 MB Download
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
