Offset Reduction Techniques In High-speed Analog-to-digital Converters: Analysis, Design And Tradeoffs
by Pedro M. Figueiredo /
2009 / English / PDF
7.6 MB Download
Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
