Verification By Error Modeling: Using Testing Techniques In Hardware Verification (frontiers In Electronic Testing)
by Katarzyna Radecka /
2003 / English / PDF
7.8 MB Download
This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.
This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.
